The invention involves a chip arrangement having a substrate plate or board, which has at least one passage through it, into which a carrier chip is inserted. A carrier chip surface has at least one integrated conductor path that connects at least one electrical or electronic structural component, in particular a sensor, with at least one electrical connection contact.
A chip arrangement of this type has become known through obvious prior use on the market. It is used to examine biological cells, which are settled in a nutrient medium on the surface of the substrate plate and the support chip inserted therein. In the support chip of the previously known chip arrangement, a sensor is integrated, with which measurement signals are detected at the cells or the nutrient medium and can be guided further via conductor paths to a measurement device and evaluation device. So that the chip arrangement can be handled well in practice, it has proven expedient if it has a certain minimum size and is constructed, for example, as an essentially rectangular board with a size of 2.5.times.3 cm. Since semiconductor chips of this size are relatively expensive to manufacture, in the previously known chip arrangement, a carrier chip having the sensor is inserted into a substrate board made of glass. The chip arrangement can thereby be handled well, and nevertheless the dimensions of the carrier chip can be selected to be relatively small, so that the chip arrangement can be manufactured in a correspondingly cost-effective manner.
In the previously known chip arrangement, the carrier chip is inserted into the opening located in the substrate board in such a way that the surface of the carrier chip, which has the conductor paths, essentially connects in a flush manner onto a flat-sided surface of the substrate board, which also has conductor paths. For this purpose, the conductor paths of the carrier chips are connected via bonding compounds to those of the substrate board. The conductor paths of the substrate board lead to connection contacts which are connectable to a measurement and evaluation device. In the area of the bonding compounds of the conductor paths, bonding pads are arranged respectively on the carrier chip and on the substrate board.
So that the conductor paths of the carrier chip are electrically insulated from a medium to be examined, for example a nutrient medium with biological cells, they are covered with a passivation layer, which is applied in the manufacture of the carrier chip using masking technology. Since the bonding pads must be accessible when applying the bonding compounds that connect the carrier chip with the substrate board, the passivation layer has a recess in the respective area of the bonding pad. The bonding pads are therefore poured, after application of the bonding compounds, into an electrically insulating plastic mass, which encloses the bonding pads and the bonding compounds applied on them. This sealing of the bonding pads with plastic has, however, proven to be of little reliability in practice, since the nutrient medium for the cells to be examined, which is located in the area of the sensor in the use position of the chip arrangement, contains ions and salts which can infiltrate the plastic mass. A gap thereby forms between the plastic mass and the substrate board, through which the ions or salts can reach the bonding pads. Here, the danger exists on the one hand, that leak currents, which falsify the measurement signals, form between the bonding pads and the nutrient medium, and on the other hand, the salts and ions contained in the nutrient medium also cause, however, corrosion on the bonding pads, which reduces the lifetime of the chip arrangement.
From Japanese published patent application (kokai) JP 07103934 A, a chip arrangement is also already known, in which the carrier chip lies flat, with its rear side facing away from the electrical structural component, on the flat-sided surface of a substrate board and is connected to it. Here, the electrical connection between the carrier chip and the substrate board is made using a through-contact penetrating the substrate board, which leads from the rear side of the carrier chip to the rear flat side of the substrate board that faces away from the carrier chip. The connection lines to a measurement and evaluation device can thus be connected to the rear side of the substrate board that is facing away from the medium to be examined, whereby corrosion formation on the bonding pads and/or conductor paths is prevented. It is unfavorable, however, in this process, that the through-contact can only be realized with a relatively large production engineering expense, which is why the manufacture of the chip arrangement is comparatively time-intensive and expensive.